Some semiconductor memories (e.g., dynamic random access memory (DRAM)) may require periodic refresh operations to maintain data stored therein. A memory device typically sequentially refreshes portions of a memory. A portion of memory may include a word line, a plurality of word lines, a memory array, a plurality of arrays, and/or another sub-set of the memory. The portions of the memory may be associated with refresh addresses. A refresh address counter included in the memory may be used to generate internal refresh addresses in turn to ensure all portions of the memory are refreshed, for example, during self-refresh. The refresh address counter may be a binary counter, and the number of refresh addresses generated by the refresh address counter may be an Nth power of 2.
Some memories may have memory configurations such that the number of portions to be assigned a refresh address is not an Nth power of 2. In memory devices including these memories, the binary address counter may produce refresh addresses to which no portion of the memory is assigned. This may cause wasteful time gaps in the refresh operations in the memory device and/or poor distribution of current in the memory device.